Electronic Design

Layout-Dependent Modeling Boosts CMOS Gate Density

A layout-dependent circuit-design model from Toshiba helps boost gate density and improve cost-performance in next-generation 45-nm CMOS technology. More specifically, 45-nm CMOS gate density can be 2 ...
Electronic Design

Design Crystal Oscillators With CMOS Gates

Using CMOS Gates to create crystal oscillators is cost-effective and gives the designer more control over the parameters. To view the application note, click on the URL below. Circuit selected for www ...
EDN

Detect wire breaks with unusual CMOS gate circuit

CMOS devices have large input impedance with input currents on the order of 0.01nA. Adding feedback circuitry can result in a latch-like device that can be used to store bits, and also operate in a ...
Design-Reuse

Low Power Universal Gates for Approximate Computing

Density and speed of IC’s have increased exponentially for several decades, following a trend described by Moore’s Law. While it is accepted that this exponential improvement trend will end, it is ...
Design-Reuse

Lessons learned from extending 0.12 um CMOS for multimillion gate, IP designs

Complexity is very high with multimillion-gate, IP rich designs in CMOS12, involving many components in the nanometer SoC manufacturing chain. Achieving First Time Silicon Success (FTSS) requires a ...
EDN

Spare cell leakage minimization in physical design, part 1 of 2

Leakage in IC designs constitutes a significant amount of power dissipation because CMOS gates are not ideal switches. The leakage in CMOS gates varies significantly for different combinations of ...
Electronics Weekly

Novel logic aims to beat CMOS, on 10 year older fabs

Nottingham-based SFN (Search for the Next) has characterised its novel transistor-based logic, and claims that it matches CMOS performance even when made in older fabs. It would “enable chip designers ...