EDN

3-bit Flash ADC [Cadence ICFB, 0.5μmCMOS]

Designed a 3-bit Flash Analog to Digital Converter using Sample and Hold Circuit. The design was extended to 4-bit Flash ADC and it was sent to MOSIS for chip fabrication. The chip was tested to ...
Nature

An energy-efficient Flash-SAR ADC with two-step flash structure in a 0.18 μm CMOS process

With the increasing performance requirements for data acquisition in applications such as the Internet of things and artificial intelligence, analog-to-digital converters (ADCs) face stringent ...
Nature

Design and test of analog-to-digital converters with enhanced test strategies using built in self test

Analog and Mixed Signal Integrated Circuits (AMS ICs), which have many different components on a single chip, can now be integrated due to technological advancements. However, controllability and ...
EDN

112-Gbps LR SerDes PHY Taps CTLE and Time Interleaved Flash ADC to Reduce ADC Resolution

The right balance of CTLE circuitry and flash ADC sizes and number play a key role in minimizing ADC bits to achieve minimum area and power. The design of a state-of-the-art 112-gigabits-per-second ...